Cadence

Cadence and ARC have optimized and integrated the Cadence® Encounter® digital IC design platform for the patented ARChitect™ Processor Configurator tool. ARC customers now can easily produce RTL, synthesis, and floorplanning scripts that are tuned to Encounter from within the ARChitect environment. This process helps SoC designers better anticipate the behavior of electrical signals and ensure the design is fully verified before going to silicon.

Driven by the need for more energy efficient SoC’s to enable emerging mobile devices, Cadence and ARC are focused on the joint development of technologies to reduce power consumption.  Cadence and ARC recently introduced an automated low-power reference design methodology (LP-RDM) that is fully integrated with the  ARChitect Processor Configurator. Based on the industry-standard Common Power Format (CPF), this LP-RDM together with the Cadence® Low Power Solution ensures that the advanced power management techniques embodied in ARC's new Energy PRO technology are captured in RTL and implemented consistently throughout the design flow to GDSII. Users of the reference design flow may achieve up to a four-fold reduction of IP core power.  For more information download the New Low Power RDM for Energy PRO Technology reference manual.

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